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کامپیوتر و شبکه::
سلول جمعکننده
delay of a full adder cell is obtained from the latency of a XOR gate added to delay of an AND gate and an OR gate, that is 3.5 unit delay.
To implement the proposed three-operand multiplier applying nanotube technology, an AND gate and a full adder cell, presented by Reshadinezhad et al
The AND gate and the full adder cell designed in CNFET technology, are depicted in Fig. 6.
(a) AND Gate Using CNFET, (b) Full Adder Cell Based on Carbon Nanotube Technology [23]
To implement the proposed multiplier, an AND gate, a full adder cell and a (4:2) compressor based on CNFET are simulated.
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